An Efficient Design Approach for Low Leakage with NBTI Aware Analysis

As the technology scales down the leakage current in the circuit increases due to reduction in threshold voltage and Negative Bias Temperature Instability (NBTI) producing aging effect in the circuit. Leakage current and NBTI strongly depends on Input Vector Control Technique (IVC) , but IVC is not effective for larger circuits. Therefore in this paper two new designs (1)Ultra low power diode based technique with body biasing on both sleep pMOS transistors and (2)Ultra low power diode based technique with Parallel sleep pMOS and body biasing on all sleep pMOS to reduce leakage and delay of the circuit and a third design (3)Ultra low power diode based technique with delay on parallel sleep pMOS and Body Biasing on all sleep pMOS for reducing NBTI degradation of the circuit are proposed. Experimentations are done on 1 bit full adder circuit at 90nm technology node and supply voltage 1V.The results reveal that leakage current reduces by 81.73% using Ultra low power diode based technique with body biasing on both sleep pMOS transistors and 81.76% by using Ultra low power diode base technique with Parallel pMOS and body biasing on all sleep pMOS transistors and delay reduces by 15.31% and 15.41% respectively of the circuit.